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DATA SHEET
MOS INTEGRATED CIRCUIT
PD8861
5400 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The PD8861 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD8861 has 3 rows of 5400 pixels, and each row has a single-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
* Valid photocell * Photocell pitch * Photocell size * Line spacing * Color filter * Resolution : * Data rate * Power supply * On-chip circuits :: : 5400 pixels x 3 : 5.25 m 2 : 5.25 x 5.25 m : 42 m (8 lines) Red line - Green line, Green line - Blue line : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx*hour) : 24 dot/mm A4 (210 x 297 mm) size (shorter side) 600 dpi US letter (8.5" x 11") size (shorter side) : 6 MHz Max. : +12 V : Reset feed-through level clamp circuits Voltage amplifiers
7
* Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number Package CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
PD8861CY
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S15167EJ2V0DS00 (2nd edition) Date Published June 2001 NS CP (K) Printed in Japan
The mark
shows major revised points.
(c)
2000
PD8861
BLOCK DIAGRAM
VOD 20 GND 2 GND 11
S5399 S5400 D65 D66 D67
2
15
1
14
D14
D64 S1 S2
******
Photocell (Blue)
VOUT1 (Blue)
Transfer gate 21 CCD analog shift register
S5399 S5400 D65 D66 D67
13
TG1 (Blue)
D14
D64 S1 S2
******
Photocell (Green)
VOUT2 (Green)
Transfer gate 22 CCD analog shift register
S5399 S5400 D65 D66 D67
12
TG2 (Green)
D14
D64 S1 S2
******
Photocell (Red)
VOUT3 (Red)
1
Transfer gate CCD analog shift register
10
TG3 (Red)
4
3
5
8
9
CLB
RB
1L
2
1
2
Data Sheet S15167EJ2V0DS
PD8861
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) * PD8861CY
Output signal 3 (Red) Ground Reset gate clock Reset feed-through level clamp clock Last stage shift register clock 1 No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock 3 (for Red) Ground
VOUT3 GND
1 2
22 21
VOUT2 VOUT1 VOD NC NC NC NC
Output signal 2 (Green) Output signal 1 (Blue) Output drain voltage No connection No connection No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock 1 (for Blue) Transfer gate clock 2 (for Green)
1
1
RB
3 4 5 6 7 8 9 10 11
1
20 19 18 17 16 15 14 13 12
CLB
1L
NC NC
Green
2 1
Blue
Red
2 1 TG1 TG2
5400
5400
GND
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25 m 2.75 m 2.5 m
5400
TG3
Blue photocell array 8 lines (42 m)
5.25 m
5.25 m Channel stopper
Green photocell array 8 lines (42 m)
5.25 m Aluminum shield
Red photocell array
Data Sheet S15167EJ2V0DS
3
PD8861
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature V TG1 to V TG3 TA Tstg -0.3 to +8 0 to +60 -40 to +70 V C C VOD V 1, V 2, V 1L V RB V CLB Symbol Ratings -0.3 to +15 -0.3 to +8 -0.3 to +8 -0.3 to +8 Unit V V V V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high level Transfer gate clock low level Data rate V TG1H to V TG3H V TG1L to V TG3L f RB 4.5 -0.3 - V 1H 0 1.0
Note
Symbol VOD V 1H, V 2H, V 1LH V 1L, V 2L, V 1LL V RBH V RBL V CLBH
Min. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3
Typ. 12.0 5.0 0 5.0 0 5.0
Max. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 V 1H
Note
Unit V V V V V V
V CLBL
0
V
V V MHz
+0.3 6.0
Note When Transfer gate clock high level (V TG1H to V TG3H) is higher than Shift register clock high level (V 1H), Image lag can increase.
4
Data Sheet S15167EJ2V0DS
PD8861
ELECTRICAL CHARACTERISTICS
TA = +25C, VOD = 12 V, data rate (f RB) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Saturation voltage Saturation exposure Red Green Blue Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Red Green Blue Image lag Offset level
Note 1 Note 2
Symbol Vsat SER SEG SEB PRNU ADS DSNU PW ZO RR RG RB IL VOS td TTE Red Green Blue
Test Conditions
Min. 2.0 - - - - - - - - 4.15 4.07 2.36
Typ. 2.5 0.420 0.429 0.739 6 0.2 1.5 360 0.35 5.94 5.82 3.38 1.5 5.5 25 98 630 540 460 1666 2777 750 0.9
Max. - - - - 20 2.0 5.0 540 1 7.72 7.57 4.39 7.0 7.0 - - - - - - - 1500 -
Unit V lx*s lx*s lx*s % mV mV mW k V/lx*s V/lx*s V/lx*s % V ns % nm nm nm times times mV mV
VOUT = 1.0 V Light shielding Light shielding
VOUT = 1.0 V
- 4.0 - 92 - - - - - 0 -
Output fall delay time
VOUT = 1.0 V VOUT = 1.0 V, data rate = 6 MHz
Total transfer efficiency Response peak
Dynamic range
Note 1
DR1 DR2
Vsat/DSNU Vsat/ CDS Light shielding Light shielding, bit clamp mode
Reset feed-through noise Random noise (CDS)
RFTN
CDS
Notes 1. Refer to TIMING CHART 2, 3. 2. When the fall time of 1L (t1') is the Typ. value (refer to TIMING CHART 2, 3).
Data Sheet S15167EJ2V0DS
5
PD8861
INPUT PIN CAPACITANCE (TA = +25C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol C 1 Pin name Pin No. 9 14 Shift register clock pin capacitance 2 C 2 Min. - - - - - - - - - - Typ. 300 300 300 300 10 10 10 100 100 100 Max. - - - - - - - - - - Unit pF pF pF pF pF pF pF pF pF pF
1 2 1L RB CLB TG1 TG2 TG3
8 15
Last stage shift register clock pin capacitance Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance
C L C RB C CLB C TG
5 3 4 13 12 10
Remark Pin 9 and 14 ( 1), 8 and 15 ( 2) are each connected inside of the device.
6
Data Sheet S15167EJ2V0DS
TIMING CHART 1 (for each color)
TG1 to TG3 1 2
1L RB
Data Sheet S15167EJ2V0DS
Note
Note
CLB (Bit clamp mode) CLB (Line clamp mode)
5463 5464 5465 5466 5467 5468 5469
Invalid photocell (3 pixels)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VOUT1 to VOUT3
Optical black (49 pixels)
Invalid photocell (2 pixels)
Note Set the RB and CLB (Bit clamp mode) to high level during this period. And stop the RB pulse while the CLB pulse is low level at line clamp mode. Remark Inverse pulse of the TG1 to TG3 can be used as CLB at line clamp mode. 7
61 62 63 64 65 66
Valid photocell (5400 pixels)
PD8861
PD8861
TIMING CHART 2 (Bit clamp mode, for each color)
t1 t2
1
90% 10%
2
90% 10% t1' t2'
1L
t5 t6
90% 10% t3 t4
RB
90% 10% t7 90% 10% td RFTN t9 t8 t10 t11
CLB
VOUT VOS 10%
Symbol t1, t2 t1', t2' t3 t4 t5, t6 t7 t8 t9, t10 t11
Min. 0 0 20 40 0 -5
Note
Typ. 25 5 200 300 5 50 200 5 50
Max. - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns
35 0 10
Note Min. of t7 shows that the RB and CLB overlap each other.
90%
RB
t7
CLB
90%
8
Data Sheet S15167EJ2V0DS
PD8861
TIMING CHART 3 (Line clamp mode, for each color)
t1 t2
1
90% 10%
2
90% 10% t1' t2'
1L
t5 90% 10% t6
90% 10% t3 t4
RB
CLB
"H"
td RFTN
VOUT VOS 10%
Symbol t1, t2 t1', t2' t3 t4 t5, t6
Min. 0 0 20 40 0
Typ. 25 5 200 300 5
Max. - - - - -
Unit ns ns ns ns ns
Data Sheet S15167EJ2V0DS
9
PD8861
TIMING CHART 4
t13 t12 t14
TG1 to TG3
90% 10% t15 90%
t16
1 2
1L
90% t17 Note 1 t18
RB
90% t7 t11
CLB (Bit clamp mode)
90% t22 t20 Note 2 t21 t23
CLB (Line clamp mode)
90% 10% t9 t19 t10
Symbol t7 t9, t10 t11 t12 t13, t14 t15, t16 t17, t18 t19 t20, t21 t22, t23
Min. -5
Note 3
Typ. 50 5 50 10000 50 1000 400 t12 50 350
Max. - - - 50000 - - - 50000 - -
Unit ns ns ns ns ns ns ns ns ns ns
0 10 3000 0 900 200 t12 0 0
Notes 1. Set the RB and CLB (Bit clamp mode) to high level during this period. 2. Stop the RB pulse during this period. 3. Min. of t7 shows that the RB and CLB overlap each other. Remark Inverse pulse of the TG1 to TG3 can be used as CLB.
10
Data Sheet S15167EJ2V0DS
PD8861
1, 2 cross points
1
1.0 V to 4.0 V 1.0 V to 4.0 V
2
1L, 2 cross points
2
2.0 V or more 0.5 V or more
1L
Remark Adjust cross points ( 1, 2) and ( 1L, 2) with input resistance of each pin.
Data Sheet S15167EJ2V0DS
11
PD8861
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
PRNU (%) =
x x 100 x
x : maximum of xj - x
5400 j=1
xj
x=
5400
xj : Output voltage of valid pixel number j
VOUT
Register Dark DC level
x
x
4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
5400 j=1
dj
dj : Dark signal of valid pixel number j
ADS (mV) =
5400
12
Data Sheet S15167EJ2V0DS
PD8861
5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of dj - ADS j = 1 to 5400 dj : Dark signal of valid pixel number j
VOUT ADS Register Dark DC level DSNU
6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light ON OFF
VOUT V1 VOUT
IL (%) =
V1 x 100 VOUT
Data Sheet S15167EJ2V0DS
13
PD8861
9. Random noise (CDS) : CDS Random noise CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get "VDi". 3. The output level is measured during the video output time averaged over 100 ns to get "VOi". 4. The correlated double sampling output is defined by the following formula. VCDSi = VDi - VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation CDS using the following formula equation.
100
CDS (mV) =
i=1
(VCDSi - V)
100
2
, V=
1
100
100 i = 1
VCDSi
Reset feed-through
Video output
14
Data Sheet S15167EJ2V0DS
PD8861
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE CHARACTERISTIC
8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25C)
4
Relative Output Voltage
2
1
0.5
Relative Output Voltage
10 20 30 40 50
1
0.25
0.2
0.1 0
0.1
1
5 Storage Time (ms)
10
Operating Ambient Temperature TA (C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25C)
100 R
B 80
G
Response Ratio (%)
60
40
G 20
B 0 400 500 600 Wavelength (nm) 700 800
Data Sheet S15167EJ2V0DS
15
PD8861
APPLICATION CIRCUIT EXAMPLE
+5 V
+ 1 2 47 3 4 5 6 7 4.7 4.7 10 8 9 10 11
PD8861
B3 VOUT3 GND VOUT2 VOUT1 VOD NC NC NC NC 22 21 20 + 19 18 17 16 0.1 F 10 F/16 V 15 14 13 12 4.7 4.7 10 10 0.1 F 10 F/16 V +5 V B2 +12 V B1
10 F/16 V 0.1 F
RB CLB
47 150
RB
CLB 1L
NC NC
+
2
2
2 1 TG1 TG2
1 TG3
GND
1 TG
Remark The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (2 MHz data rate < 6 MHz).
B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 CCD VOUT 100 2SC945 47 F/25 V
2 k
16
Data Sheet S15167EJ2V0DS
PD8861
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))
(Unit : mm) 1bit 0.50.3
37.5 44.00.3
9.250.3
2.0
10.16
(1.79)
2.550.2 1 1.020.15 0.460.1 25.4 2.54 (5.42) 4.210.5 4.390.4
0 10
0.25
0.05
Name Plastic cap
Dimensions 42.9 x 8.35 x 0.7
2
Refractive index 1.5
1 The bottom of the package
The surface of the chip
2 The thickness of the cap over the chip 22C-1CCD-PKG6-1
Data Sheet S15167EJ2V0DS
17
PD8861
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (C10535E). Type of Through-hole Device
PD8861CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process Partial heating method Conditions Pin temperature : 300 C or below, Heat time : 3 seconds or less (per pin)
Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact.
18
Data Sheet S15167EJ2V0DS
PD8861
NOTES ON CLEANING THE PLASTIC CAP
1 CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
2 RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent.
Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone
Symbol EtOH MeOH IPA NMP
Data Sheet S15167EJ2V0DS
19
PD8861
[MEMO]
20
Data Sheet S15167EJ2V0DS
PD8861
[MEMO]
Data Sheet S15167EJ2V0DS
21
PD8861
[MEMO]
22
Data Sheet S15167EJ2V0DS
PD8861
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15167EJ2V0DS
23
PD8861
* The information in this document is current as of June, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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